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features complete cmos stereo a/d system delta-sigma a/d converters digital anti-alias filtering s/h circuitry and voltage reference adjustable system sampling rates including 32khz, 44.1 khz & 48khz low noise and distortion >90 db s/(n+d) internal 64x oversampling linear phase digital anti-alias filtering 0.01db passband ripple 80db stopband rejection low power dissipation: 400 mw power-down mode for portable applications evaluation board available general description the cs5336, cs5338 & cs5339 are complete analog- to-digital converters for stereo digital audio systems. they perform sampling, analog-to-digital conversion and anti-aliasing filtering, generating 16-bit values for both left and right inputs in serial form. the output word rate can be up to 50 khz per channel. the adcs use delta-sigma modulation with 64x over- sampling, followed by digital filtering and decimation, which removes the need for an external anti-alias filter. the cs5336 & cs5338 have an sclk which clocks out data on rising edges. the cs5339 has an sclk which clocks out data on falling edges. the cs5336 has a filter passband of dc to 22khz. the cs5338 & cs5339 have a filter passband of dc to 24 khz. the filters have linear phase, 0.01 db passband ripple, and >80 db stopband rejection. the adcs are housed in a 0.6" wide 28-pin plastic dip, and also in a 0.3" wide 28-pin soic surface mount package. extended temperature range versions of the cs5336 are also available. ordering information: see page 3-59 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445-7222 fax: (512) 445-7581 aug 93 ds23f1 3-39 16-bit, stereo a/d converters for digital audio semiconductor corporation ainr s/h agnd dac ainl s/h dac serial output interface voltage reference vref calibration sram comparator comparator lp filter lp filter zerol zeror 27 26 2 3 1 28 vd+ 18 dgnd 19 17 va- 5 vl+ 25 va+ 4 smode 13 nc 22 nc 8 tst 11 sclk 15 apd 6 acal 7 ic lk a 23 dpd 10 dcal 9 lgnd 24 digital decimation filter digital decimation filter calibration microcontroller l/r 14 fsync sdata 16 cmode 12 ic lkd 20 oclkd 21 cs5336 cs5338 cs5339
cs5336,8,9-k cs5336-b cs5336-t parameter symbol min typ max min typ max min typ max units specified temperature range t a 0 to 70 -40 to +85 -55 to +125 c resolution 16 - - 16 - - 16 - - bits dynamic performance dynamic range 92.7 95.7 - 90 93.5 - 84 92 - db signal-to-(noise + distortion); thd+n s/(n+d) 90.7 92.7 - 85 89 - 82 86 - db signal to peak noise - 96 - - 95 - - 94 - db total harmonic distortion thd .0025 .001 - .005 .001 - .013 .005 - % interchannel phase deviation - .0001 - - .0001 - - .0001 - interchannel isolation (dc to 20 khz) 100 106 - 90 106 - 83 96 - db dc accuracy interchannel gain mismatch - 0.01 0.05 - .01 .05 - .01 0.1 db gain error (includes vref tolerance) - 1 5- 2 5- 3 6% gain drift (includes vref drift, note 1) - 25 - - 70 - - 70 - ppm/ c bipolar offset error (note 2) - 5 15 - 10 30 - 16 65 lsb offset drift (note1) - 15 - - 20 - - 20 - ppm/ c analog characteristics (logic 0 = gnd; logic 1 = vd+; k grade: t a = 25 c; b and t grades: t a = t min to t max ; va+, vl+,vd+ = 5v; va- = -5v; full-scale input sinewave, 1khz; output word rate = 48 khz; sclk = 3.072 mhz; source impedance = 50 w with 10 nf to agnd; measurement bandwidth is 10 hz to 20 khz; unless otherwise specified.) analog input input voltage range ( full scale) vin 3.5 3.68 - -3.5 3.68 - 3.5 3.68 - v input impedance zin - 65 - - 65 - - 65 - k w power supplies power supply current (va+)+(vl+) ia+ - 25 35 - 25 35 - 25 35 ma with apd, dpd low va- ia- - -25 -35 - -25 -35 - -25 -35 ma (normal operation) vd+ id+ - 30 45 - 30 45 - 30 50 ma power supply current (va+)+(vl+) ia+ - 10 50 - 10 50 - 10 50 m a with apd, dpd high va- ia- - -10 -50 - -10 -50 - -10 -50 m a (power-down mode) vd+ id+ - 10 400 - 10 400 - 10 400 m a power consumption (apd, dpd low) pdn - 400 575 - 400 575 - 400 600 mw (apd, dpd high) pds - 0.15 2.5 - 0.15 2.5 - 0.15 2.5 mw power supply (dc to 26 khz) psrr -54- -54- -54- db rejection ratio (26 khz to 3.046 mhz) - 100 - - 100 - - 100 - db notes: 1. this parameter is guaranteed by design and/or characterization. 2. after calibration with dcal connected to acal, and zerol & zeror terminated to agnd with an impedance matched to the ainr & ainl source impedance. executing a calibration with acal tied low (see power down and offset calibration section) will yield an offset error of typically less than 5lsb. specifications are subject to change without notice. cs5336, cs5338, cs5339 3-40 ds23f1
units typ min symbol parameter max v v - - - v oh v ol high-level output voltage at io = -20ua low-level output voltage at io = 20ua - 0.1 ua 1.0 - iin input leakage current v v - - 70%vd+ - v il v ih low-level input voltage high-level input voltage - 30% vd+ 4.4 - digital filter characteristics (t a = 25 c; va+, vl+ ,vd+ = 5v 5%; va- = -5v 5%; output word rate of 48 khz) digital characteristics (t a = 25 c; va+, vl+ ,vd+ = 5v 5%; va- = -5v 5%) parameter units typ symbol min max passband ripple 0.01 db passband khz khz stopband cs5336 cs5338, cs5339 26 3046 28 3044 khz khz stopband attenuation 80 db (note 3) group delay (owr = output word rate) 18/owr s group delay variation vs. frequency 0.0 us t gd t gd 0 22 khz 0 24 khz cs5336 cs5338, cs5339 (-3 db) (-3 db) 0 20 0 22 cs5336 cs5338, cs5339 (-0.01 db) (-0.01 db) to to to to - - to to -- - - -- + _ notes: 3. the analog modulator samples the input at 3.072mhz for an output word rate of 48 khz. there is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 3.072mhz 22khz for the cs5338 & cs5339, or n x 3.072mhz 20.0khz for the cs5336, where n = 0,1,2,3...). absolute maximum ratings (agnd, lgnd, dgnd = 0v, all voltages with respect to gnd) parameter input current, any pin except supplies dc power supplies: analog input voltage (ain and zero pins) digital input voltage storage temperature ambient temperature (power applied) ma units v v c c positive logic v positive digital v negative analog positive analog v v min - (va- )- 0.3 -0.3 -0.3 +0.3 -0.3 -0.3 -55 -65 symbol i in v ina v ind t a t stg vl+ vd+ va+ va- max +150 +125 (va+ )+ 0.3 (vd+) + 0.3 (va+) + 0.3 +6.0 -6.0 +6.0 + _ 10 warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. cs5336, cs5338, cs5339 ds23f1 3-41
parameter symbol min typ max unit iclkd period (cmode low) (note 6) t clkw1 78 - 3906 ns iclkd low (cmode low) t clkl1 31 - - ns iclkd high (cmode low) t clkh1 31 - - ns iclkd rising to oclkd rising (cmode low) t io1 5 - 40 ns iclkd period (cmode high) t clkw2 52 - 2604 ns iclkd low (cmode high) t clkl2 20 - - ns iclkd high (cmode high) t clkh2 20 - - ns iclkd rising or falling to oclkd rising (cmode high, note 4) t io2 5 - 45 ns iclkd rising to l/ r edge (cmode low, master mode) t ilr1 5 - 50 ns iclkd rising to fsync edge (cmode low, master mode) t ifs1 5 - 50 ns iclkd rising to sclk edge (cmode low, master mode) t isclk1 5 - 50 ns iclkd falling to l/ r edge (cmode high, master mode) t ilr2 5 - 50 ns iclkd falling to fsync edge (cmode high, master mode) t ifs2 5 - 50 ns iclkd falling to sclk edge (cmode high, master mode) t isclk2 5 - 50 ns sclk rising to sdata valid (master mode, note 5) t sdo 0 - 50 ns sclk duty cycle (master mode) 40 50 60 % sclk rising to l/ r (master mode, note 5) t mslr -20 - 20 ns sclk rising to fsync (master mode, note 5) t msfs -20 - 20 ns sclk period (slave mode) t sclkw 155 - - ns sclk pulse width low (slave mode) t sclkl 60 - - ns sclk pulse width high (slave mode) t sclkh 60 - - ns sclk rising to sdata valid (slave mode, note 5) t dss - - 50 ns l/ r edge to msb valid (slave mode) t lrdss - - 50 ns falling sclk to l/ r edge delay (slave mode, note 5) t slr1 30 - - ns l/ r edge to falling sclk setup time (slave mode, note 5) t slr2 30 - - ns falling sclk to rising fsync delay (slave mode, note 5) t sfs1 30 - - ns rising fsync to falling sclk setup time (slave mode, note 5) t sfs2 30 - - ns dpd pulse width t pdw 2 x tclkw - - ns dpd rising to dcal rising t pcr - - 50 ns dpd falling to dcal falling (owr = output word rate) t pcf -4096-1/owr switching characteristics (t a = 25 c; va+, vl+, vd+ = 5v 5%; va- = -5v 5%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 20 pf) notes: 4. iclkd rising or falling depends on dpd to l/ r timing (see figure 2). 5. sclk is shown for cs5336, cs5338. sclk is inverted for cs5339. 6. specifies minimum output word rate (owr) of 1 khz. cs5336, cs5338, cs5339 3-42 ds23f1
iclkd clkh t clkl t t clkw1 oclkd (cmode low) t io1 sdata sclk input (slave mode) (slave mode) l/r input sclk input (slave mode) fsync input (slave mode) sdata t ilr1 fsync output t ifs1 sclk output t isclk1 (master mode) l/r output (master mode) (master mode) sclk output (master mode) t mslr sdata t sdo t msfs sclkl t dss t msb msb-1 msb-2 lrdss t sclkh t slr1 t slr2 t t sclkw msb msb-1 msb-2 sfs1 t sfs2 t l/ r output (master mode) fsync output (master mode) iclkd clkh2 t clkl2 t t clkw2 t ilr2 t ifs2 t isclk2 dpd t io2 oclkd (cmode high) fsync output sclk output (master mode) l/r output (master mode) (master mode) dcal pdw t pcr t pcf t iclkd to outputs propagation delays (cmode low) sclk to sdata, l/ r & fsync - master mode sclk to l/ r & sdata - slave mode, fsync high fsync to sclk - slave mode, fsync controlled. power down & calibration timing iclkd to outputs propagation delays (cmode high) cs5336, cs5338, cs5339 ds23f1 3-43
audio data processor cs5336 vref ainl ainr zerol zeror agnd nc nc va+ va- vl+ vd+ apd dpd acal dcal tst lgnd dgnd 28 2 27 3 26 1 8 22 52419 6 10 7 9 11 425 18 +5v analog 0.1 m f + 1 m f 0.1 m f control 0.1 m f 1 m f -5v analog 10 nf 10 nf 0.1 m f left analog input right analog input a/d converter 10 m f + 0.1 m f 1 m f + + ferrite bead 51 w 51 w 51 w va+ sclk 14 15 l/r sdata 16 cs5338 cs5339 ferrite bead may be used if vd+ is +5v digital power down & calibrate mode settings smode cmode 13 12 timing logic fsync 17 & clock iclkd 20 21 23 oclkd iclka derived from va+. an example ferrite bead is permag vk200-2.5/52 if used, do not drive any other logic from vd+. figure 1. typical connection diagram recommended operating conditions (agnd, lgnd, dgnd = 0v; all voltages with respect to ground) dc power supplies: v parameter symbol min typ max units positive digital positive logic positive analog negative analog v v v vd+ vl+ va+ va- 4.75 4.75 analog input voltage 3.68 3.68 - v v ain 4.75 4.75 _ 5.0 5.0 5.0 5.0 _ 5.25 5.25 _ va+ _ (note 7) va+ notes: 7. the adcs accept input voltages up to the analog supplies (va+, va-). they will produce a positive full-scale output for inputs above 3.68 v and negative full-scale output for inputs below -3.68 v. these values are subject to the gain error tolerance specification. additional tag bits are output to indicate the amount of overdrive. cs5336, cs5338, cs5339 3-44 ds23f1
general description the cs5336, cs5338, and cs5339 are 16-bit, 2- channel a/d converters designed specifically for stereo digital audio applications. the devices use two one-bit delta-sigma modulators which simul- taneously sample the analog input signals at a 64 x sampling rate. the resulting serial bit streams are digitally filtered, yielding pairs of 16-bit val- ues. this technique yields nearly ideal conversion performance independent of input frequency and amplitude. the converters do not require difficult- to-design or expensive anti-alias filters, and do not require external sample-and-hold amplifiers or a voltage reference. an on-chip voltage reference provides for an in- put signal range of 3.68 volts. any zero offset is internally calibrated out during a power-up self- calibration cycle. output data is available in serial form, coded as 2s complement 16-bit numbers. typical power consumption of only 400 mw can be further reduced by use of the power-down mode. for more information on delta-sigma modulation and the particular implementation inside these adcs, see the references at the end of this data sheet. system design very few external components are required to sup- port the adc. normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for anti-aliasing are all thats required, as shown in figure 1. master clock input the master input clock (iclkd) into the adc runs the digital filter, and is used to generate the modulator sampling clock. iclkd frequency is determined by the desired output word rate (owr) and the setting of the cmode pin. cmode high will set the required iclkd fre- quency to 384 x owr, while cmode low will set the required iclkd frequency to 256 x owr. table 1 shows some common clock fre- quencies. the digital output clock (oclkd) is always equal to 128 x owr, which is always 2 x the input sample rate. oclkd should be connected to iclka, which controls the input sample rate. the phase alignment between iclkd and oclkd is determined as follows: when cmode is oclkd/ l/ r cmode iclkd iclka sclk (khz) (mhz) (mhz) (mhz) 32 low 8.192 4.096 2.048 32 high 12.288 4.096 2.048 44.1 low 11.2896 5.6448 2.8224 44.1 high 16.9344 5.6448 2.8224 48 low 12.288 6.144 3.072 48 high 18.432 6.144 3.072 table 1. common clock frequencies figure 2. iclkd to oclkd timing with cmode high (384 x owr) * 01234567 ** *** 1 2 1 2 input l/ r _ input dpd output oclkd input l/ r _ output oclkd input iclkd * dpd low is recognized on the next iclkd rising edge (#0) ** l/ r rising before iclkd rising #2 causes oclkd -1 *** l/ r rising after iclkd rising #2 causes oclkd - 2 cs5336, cs5338, cs5339 ds23f1 3-45
low, iclkd is divided by 2 to generate oclkd. the phase relationship between iclkd and oclkd is always the same, and is shown in the switching characteristics timing diagrams. when cmode is high, oclkd is iclkd di- vided by 3. there are two possible phase relationships between iclkd and oclkd, which depend on the start-up timing between dpd and l/ r, shown in figure 2. serial data interface the serial data output interface has 3 possible modes of operation: master mode, slave mode with fsync high, and slave mode with fsync controlled. in master mode, the a/d converter is driven from a master clock (iclkd) and outputs all other clocks, derived from iclkd (see figure 3). notice the one sclk cycle delay between l/ r edges and fsync rising edges. fsync brackets the 16 data bits for each chan- nel. in slave mode, l/ r and sclk are inputs. l/ r must be externally derived from iclkd, and should be equal to the output word rate. sclk should be equal to the input sample rate, which is equal to oclkd/2. other sclk frequencies are possible, but may degrade dynamic range because of interference effects. data bits are clocked out via the sdata pin using the sclk and l/ r in- puts. the rising edge of sclk causes the adc to output 0 1 2 3 16 17 18 19 20 21 31 0 1 2 3 16 17 18 19 20 21 31 0 1 output left audio data tag bits left data tag right audio data tag bits right data tag * sclk for cs5336/8. sclk inverted for cs5339 fsync output 15 14 1 0 t2 t1 t0 15 14 1 0 t2 t1 t0 sdata output sclk * l/ r figure 3. data output timing - master mode figure 4. data output timing - slave mode, fsync high input 0 1 2 16 17 18 19 20 31 0 1 2 16 17 18 19 20 21 31 0 1 input fsync input (high) sclk * l/ r left audio data tag bits left data tag right audio data tag bits right data tag 15 14 1 0 t2 t1 t0 15 14 1 0 t2 t1 t0 sdata output * sclk for cs5336/8. sclk inverted for cs5339 15 15 30 cs5336, cs5338, cs5339 3-46 ds23f1
output each bit, except the msb, which is clocked out by the l/ r edge. as shown in figure 4, when fsync is high, serial data bits are clocked imme- diately following the l/ r edge. in slave mode with fsync controlled, as shown in figure 5, when fsync is low, only the msb is clocked out after the l/ r edge. with fsync low, sclk is ignored. when it is desired to start clocking out data, bring fsync high which enables sclk to start clocking out data. bringing fsync low will stop the data being clocked out. this feature is particularly useful to position in time the data bits onto a common se- rial bus. the serial nature of the output data results in the left and right data words being read at different times. however, the words within an l/ r cycle represent simultaneously sampled analog inputs. in all modes, additional bits are output after the data bits: 3 tag bits and a left/right indicator. the tag bits indicate a near-to-clipping input condition for the data word to which the tag bits are at- tached. table 2 shows the relationship between input level and the tag bit values. the serial bit immediately following the tag bits is 0 for the left channel, and 1 for the right channel. the re- maining bits before the next l/ r edge will be 1s for the left channel and 0s for the right channel. normally, the tag bits are separated from the audio data by the digital signal processor. how- ever, if the tag bits are interpreted as audio data, their position below the lsb would result as a very small dc offset. in all modes, sclk is shown for the cs5336 and cs5338, where data bits are clocked out on rising edges. sclk is inverted for the cs5339. input 012 input fsync input sclk * l/ r left audio data tag bits left data right audio data tag bits right data 16 17 18 19 20 0 1 2 16 17 18 19 20 15 15 sdata output 15 14 1 0 t2 t1 t0 15 14 1 0 t2 t1 t0 15 15 tag tag ** ** *** *** * *** ** falling fsync stops sclk from clocking out sdata rising fsync enables sclk to clock out sdata sclk for cs5336/8. sclk inverted for cs5339 figure 5. data output timing - slave mode, fsync controlled table 2. tag bit definition input level t2 t1 t0 1.375 x fs 1 1 1 1.250 x fs to 1.375 x fs 1 1 0 1.125 x fs to 1.250 x fs 1 0 1 1.000 x fs to 1.125 x fs 1 0 0 -1.006db to 0.000db 0 1 1 -3.060db to -1.006db 0 1 0 -6.000db to -3.060db 0 0 1 < -6.000db 0 0 0 fs = full scale (0db) input cs5336, cs5338, cs5339 ds23f1 3-47
certain serial modes align well with various inter- face requirements. a cs5339 in master mode, with an inverted l/ r signal, generates i 2 s (philips) compatible timing. a cs5336 in mas- ter mode, using fsync, interfaces well with a motorola dsp56000. a cs5336 in slave mode emulates a cs5326 style interface, and also links up to a dsp56000 in network mode. analog connections the analog inputs are presented to the modulators via the ainr and ainl pins. the analog input signal range is determined by the internal voltage reference value, which is typically -3.68 volts. the input signal range therefore is typically 3.68 volts. the adc samples the analog inputs at 3.072 mhz for a 12.288 mhz iclkd (cmode low). for the cs5336, the digital filter rejects all noise between 26 khz and (3.072 mhz-26 khz). for the cs5338 and cs5339, the digital filter re- jects all noise between 28 khz and (3.072 mhz-28 khz). however, the filter will not reject frequencies right around 3.072 mhz (and multiples of 3.072 mhz). most audio signals do not have significant energy at 3.072 mhz. never- theless, a 51 w resistor in series with the analog input, and a 10 nf npo or cog capacitor to ground will attenuate any noise energy at 3.072 mhz, in addition to providing the optimum source impedance for the modulators. the use of capacitors which have a large voltage coefficient (such as general purpose ceramics) should be avoided since these can degrade signal linearity. if active circuitry precedes the adc, it is recom- mended that the above rc filter is placed between the active circuitry and the ainr and ainl pins. the above example frequencies scale linearly with output word rate. the on-chip voltage reference output is brought out to the vref pin. a 10 m f electrolytic capaci- tor in parallel with a 0.1 m f ceramic capacitor attached to this pin eliminates the effects of high frequency noise. note the negative value of vref when using polarized capacitors. no load current may be taken from the vref output pin. the analog input level used as zero during the offset calibration period (described later) is input on the zerol and zeror pins. typically, these pins are directly attached to agnd. for the ulti- mate in offset nulling, networks can be attached to zeror and zerol whose impedances match the impedances present on ainl and ainr. power-down and offset calibration the adc has a power-down mode wherein typi- cal consumption drops to 150 m w. in addition, exiting the power-down state initiates an offset calibration procedure. apd and dpd are the analog and digital power- down pins. when high, they place the analog and digital sections in the power-down mode. bring- ing these pins low takes the part out of power-down mode. dpd going low initiates a calibration cycle. if not using the power down feature, apd should be tied to agnd. when us- ing the power down feature, dpd and apd may be tied together if the capacitor on vref is not dcal dpd cal period (4096 x l/r clocks) (85.33 ms @ 48khz) filter delay time (~40 l/r periods) (~2 ms @ 48 khz) normal operation figure 6. initial calibration cycle timing cs5336, cs5338, cs5339 3-48 ds23f1
greater than 10 m f, as stated in the "power-up considerations" section. during the offset calibration cycle, the digital sec- tion of the part measures and stores the value of the calibration input of each channel in registers. the calibration input value is subtracted from all future outputs. the calibration input may be ob- tained from either the analog input pins (ainl and ainr) or the zero pins (zerol and zeror) depending on the state of the acal pin. with acal low, the analog input pin voltages are measured, and with acal high, the zero pin volt- ages are measured. as shown in figure 6, the dcal output is high during calibration, which takes 4096 l/ r clock cycles. if dcal is connected to the acal input, the calibration routine will measure the voltage on zeror and zerol. these should be connected directly to ground or through a network matched to that present on the analog input pins. internal offsets of each channel will thus be measured and subsequently subtracted. alternatively, acal may be permanently con- nected low and dcal utilized to control a multiplexer which grounds the users front end. in this case, the calibration routine will measure and store not only the internal offsets but also any offsets present in the front end input circuitry. during calibration, the digital output of both channels is forced to a 2s complement zero. sub- traction of the calibration input from conversions after calibration substantially reduces any power on click that might otherwise be experi- enced. a short delay of approximately 40 output words will occur following calibration for the digital filter to begin accurately tracking audio band signals. power-up considerations upon initial application of power to the supply pins, the data in the calibration registers will be indeterminate. a calibration cycle should always be initiated after application of power to replace potentially large values of data in these registers with the correct values. the modulators settle very quickly (a matter of microseconds) after the analog section is powered on, either through the application of power, or by exiting the power-down mode. the voltage refer- ence can take a much longer time to reach a final value due to the presence of large external capaci- tance on the vref pin; allow approximately 5 ms/ m f. the calibration period is long enough to allow the reference to settle for capacitor values of up to 10 m f. if a larger capacitor is used, addi- tional time between apd going low and dpd going low should be allowed for vref settling before a calibration cycle is initiated. grounding and power supply decoupling as with any high resolution converter, the adc requires careful attention to power supply and grounding arrangements if its potential perform- ance is to be realized. figure 1 shows the recommended power arrangements, with va+, va- and vl+ connected to a clean 5 v supply. vd+, which powers the digital filter, may be run from the system +5v logic supply, provided that it is not excessively noisy (< 50 mv pk-to-pk). alternatively, vd+ may be powered from va+ via a ferrite bead. in this case, no additional devices should be powered from vd+. analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the adc as possible, with the low value ceramic capacitor being the nearest. the printed circuit board layout should have sepa- rate analog and digital regions and ground planes, cs5336, cs5338, cs5339 ds23f1 3-49
with the adc straddling the boundary. all sig- nals, especially clocks, should be kept away from the vref pin in order to avoid unwanted cou- pling into the modulators. the vref decoupling capacitors, particularly the 0.1 m f, must be posi- tioned to minimize the electrical path from vref to pin 1 agnd and to minimize the path between vref and the capacitors. an evaluation board is available which demonstrates the optimum layout and power supply arrangements, as well as allow- ing fast evaluation of the adc. to minimize digital noise, connect the adc digi- tal outputs only to cmos inputs. synchronization of multiple cs5336/8/9 in systems where multiple adcs are required, care must be taken to insure that the adc internal clocks are synchronized between converters to in- sure simultaneous sampling. in the absence of this synchronization, the sampling difference could be one iclkd period which is typically 81.4 nsec for a 48 khz sample rate. slave mode synchronous sampling in the slave mode is achieved by connecting all dpd and apd pins to a single control signal and supplying the same iclkd and l/ r to all converters. master mode the internal counters of the cs5336/8/9 are reset during dpd/apd high and will start simultane- ously by insuring that the release of dpd/apd for all converters is internally latched on the same rising edge of iclkd. this can be achieved by connecting all dpd/apd pins to the same control signal and insuring that the dpd/apd falling edge occurs outside a 30 ns window either side of an iclkd rising edge. performance fft tests for fft based tests, a very pure sine wave is pre- sented to the adc, and an fft analysis is performed on the output data. the resulting spec- trum is a measure of the performance of the adc. figure 7 shows the spectral purity of the cs5336 with a 1 khz, -10 db input. notice the low noise floor, the absence of any harmonic distortion, and the dynamic range value of 95.41 db. figure 8 shows the cs5336 high frequency per- formance. the input signal is a -10 db, 9 khz sine wave. notice the small 2nd harmonic at 110 db down. figure 9 shows the low-level performance of the cs5336. notice the lack of any distortion compo- nents. traditional r-2r ladder based adcs can have problems with this test, since differential non-linearities around the zero point become very significant. figure 10 shows the same very low input amplitude performance, but at 9khz input frequency. cs5336, cs5338, cs5339 3-50 ds23f1
dnl tests a differential non-linearity test is also shown. here, the converter is presented with a linear ramp signal. the resulting output codes are counted to yield a number which is proportional to the codewidth. a plot of codewidth versus code graphically illustrates the uniformity of the codewidths. figure 11 shows the excellent differ- ential non-linearity of the cs5336. this plot displays the worst case positive and negative er- rors in each of 512 groups of 128 codes. codewidths typically are within 0.2 lsbs of ideal. a delta-sigma modulator based adc has no inherent mechanism for generating dnl errors. the residual small deviations shown in figure 11 are a result of noise. nevertheless, the perform- ance shown is extremely good, and is superior to typical r-2r ladder based designs. figure 10. cs5336 fft plot with -80 db, 9 khz input figure 8. cs5336 fft plot with -10 db, 9 khz input figure 7. cs5336 fft plot with -10 db, 1 khz input 0 4 8 12 16 20 24 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal amplitude relative to full scale (db) output word rate: 48 khz full scale: 7.3 vp-p s/(n+d): 85.41 db dynamic range: 95.41 db (dc to 20 khz) figure 9. cs5336 fft plot with -80 db, 1 khz input 0 4 8 12 16 20 24 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal amplitude relative to full scale (db) output word rate: 48 khz full scale: 7.3 vp-p s/(n+d): 16.09 db dynamic range: 96.09 db (dc to 20 khz) 0 4 8 12 16 20 24 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal amplitude relative to full scale (db) output word rate: 48 khz full scale: 7.3 vp-p s/(n+d): 15.72 db dynamic range: 95.72 db (dc to 20 khz) 0 4 8 12 16 20 24 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal amplitude relative to full scale (db) output word rate: 48 khz full scale: 7.3 vp-p s/(n+d): 85.03 db dynamic range: 95.033 db (dc to 20 khz) cs5336, cs5338, cs5339 ds23f1 3-51
digital filter figures 12 through 17 show the performance of the digital filter included in the adc. all the plots assume an output word rate of 48 khz. the filter frequency response will scale precisely with changes in output word rate. the passband ripple is flat to 0.01 db maximum. stopband rejection is greater than 80 db. figures 12,14 &16 show the cs5338 and cs5339 filter characteristics. figure 17 is an expanded view of the transition band. figures 13,15 & 17 show the cs5336 filter char- acteristics. figure 17 is an expanded view of the transition band. figure 11. cs5336 differential non-linearity plot 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 cs5336, cs5338, cs5339 3-52 ds23f1
20 21 22 23 24 25 26 27 28 input frequency (khz) magnitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 22 23 24 25 26 27 28 29 30 input frequency (khz) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 magnitude (db) figure 16. cs5338/9 digital filter transition band figure 17. cs5336 digital filter transition band 0 4 8 12 16 20 24 input frequency (khz) -0.020 -0.010 0.000 0.010 0.020 magnitude (db) 0 8 16 24 32 40 48 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 magnitude (db) figure 13. cs5336 digital filter stopband rejection 0 4 8 12 16 20 24 input frequency (khz) -0.020 -0.010 0.000 0.010 0.020 magnitude (db) figure 14. cs5338/9 digital filter passband ripple 0 8 16 24 32 40 48 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 magnitude (db) figure 12. cs5338/9 digital filter stopband rejection figure 15. cs5336 digital filter passband ripple cs5336, cs5338, cs5339 ds23f1 3-53
pin descriptions power supply connections va+ - positive analog power, pin 4. positive analog supply. nominally +5 volts. vl+ - positive logic power, pin 25. positive logic supply for the analog section. nominally +5 volts. va- - negative analog power, pin 5. negative analog supply. nominally -5 volts. agnd - analog ground, pin 1. analog ground reference. lgnd - logic ground, pin 24 ground for the logic portions of the analog section. vd+ - positive digital power, pin 18. positive supply for the digital section. nominally +5 volts. dgnd - digital ground, pin 19. digital ground for the digital section. analog inputs ainl, ainr - left and right channel analog inputs, pins 2, 27 analog input connections for the left and right input channels. nominally 3.68 volts full scale. analog ground agnd vref voltage reference output left channel analog input ainl ainr right channel analog input left channel zero input zerol zeror right channel zero input positive analog power va+ vl+ analog section logic power negative analog power va- lgnd analog section logic ground analog power down input apd iclka analog section clock input analog calibrate input acal nc no connect no connect nc oclkd digital section output clock digital calibrate output dcal iclkd digital section clock input digital power down input dpd dgnd digital ground test tst vd+ digital section positive power select clock mode cmode fsync frame sync signal select serial i/o mode smode sdata serial data output left/right select l / rsclk serial data clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cs5336, cs5338, cs5339 3-54 ds23f1
zerol, zeror - zero level inputs for left and right channels, pins 3, 26. analog zero level inputs for the left and right channels. the levels present on these pins can be used as zero during the offset calibration cycle. normally connected to agnd, optionally through networks matched to the analog input networks. analog outputs vref - voltage reference output, pin 28. nominally -3.68 volts. normally connected to a 0.1 m f ceramic capacitor in parallel with a 10 m f or larger electrolytic capacitor. note the negative output polarity. digital inputs iclka - analog section input clock, pin 23. this clock is internally divided by 2 to set the modulators sample rate. sampling rates, output rates, and digital filter characteristics scale to iclka frequency. iclka frequency is 128 x the output word rate. for example, 6.144 mhz iclka corresponds to an output word rate of 48 khz per channel. normally connected to oclkd. iclkd - digital section input clock, pin 20. this is the clock which runs the digital filter. iclkd frequency is determined by the required output word rate and by the cmode pin. if cmode is low, iclkd frequency should be 256 x the desired output word rate. if cmode is high, iclkd should be 384 x the desired output word rate. for example, with cmode low, iclkd should be 12.288 mhz for an output word rate of 48 khz. this clock also generates oclkd, which is always 128 x the output word rate. apd - analog power down, pin 6. analog section power-down command. when high, the analog circuitry is in power-down mode. apd is normally connected to dpd when using the power down feature. if power down is not used, then connect apd to agnd. dpd - digital power down, pin 10 digital section power-down command. bringing dpd high puts the digital section into power-down mode. upon returning low, the adc starts an offset calibration cycle. this takes 4096 l/ r periods (85.33 ms with a 12.288 mhz iclkd). dcal is high during the calibrate cycle and goes low upon completion. dpd is normally connected to apd when using the power down feature. a calibration cycle should always be initiated after applying power to the supply pins. acal - analog calibrate, pin 7. analog section calibration command. when high, causes the left and right channel modulator inputs to be internally connected to zerol and zeror inputs respectively. may be connected to dcal. cs5336, cs5338, cs5339 ds23f1 3-55
cmode - clock mode select, pin 12. cmode should be tied low to select an iclkd frequency of 256 x the output word rate. cmode should be tied high to select an iclkd frequency of 384 x the output word rate. smode - serial interface mode select, pin 13. smode should be tied high to select serial interface master mode, where sclk, fsync and l/ r are all outputs, generated by internal dividers operating from iclkd. smode should be tied low to select serial interface slave mode, where sclk, fsync and l/ r are all inputs. in slave mode, l/ r, fsync and sclk need to be derived from iclkd using external dividers. digital outputs sdata - serial data output, pin 16. audio data bits are presented msb first, in 2s complement format. additional tag bits, which indicate input overload and left/right channel data, are output immediately following each audio data word. dcal - digital calibrate output, pin 9. dcal rises immediately upon entering the power-down state (dpd brought high). it returns low 4096 l/ r periods after leaving the power down state (dpd brought low), indicating the end of the offset calibration cycle (which = 85.33 ms with a 12.288 mhz iclkd). may be connected to acal. oclkd - digital section output clock, pin 21. oclkd is always 128 x the output word rate. normally connected to iclka. digital inputs or outputs sclk - serial data clock, pin 15. data is clocked out on the rising edge of sclk for the cs5336 and cs5338. data is clocked out on the falling edge of sclk for the cs5339. in master mode (smode high), sclk is a continuous output clock at 64 x the output word rate. in slave mode (smode low), sclk is an input, which requires a continuously supplied clock at any frequency from 32 x to 128 x the output word rate (64 x is preferred). when fsync is high, sclk clocks out serial data, except for the msb which appears on sdata when l/ r changes. cs5336, cs5338, cs5339 3-56 ds23f1
l/ r - left/right select, pin 14. in master mode (smode high), l/ r is an output whose frequency is at the output word rate. l/ r edges occur 1 sclk cycle before fsync rises. when l/ r is high, left channel data is on sdata, except for the first sclk cycle. when l/ r is low, right channel data is on sdata, except for the first sclk cycle. the msb data bit appears on sdata one sclk cycle after l/ r changes. in slave mode (smode low), l/ r is an input which selects the left or right channel for output on sdata. the rising edge of l/ r starts the msb of the left channel data. l/ r frequency must be equal to the output word rate. although the outputs of each channel are transmitted at different times, the two words in an l/ r cycle represent simultaneously sampled analog inputs. fsync - frame synchronization signal, pin 17. in master mode (smode high), fsync is an output which goes high coincident with the start of the first sdata bit (msb) and falls low immediately after the last sdata audio data bit (lsb). in slave mode (smode low), fsync is an input which controls the clocking out of the data bits on sdata. fsync is normally tied high, which causes the data bits to be clocked out immediately following l/ r transitions. if it is desired to delay the data bits from the l/ r edge, then fsync must be low during the delay period. bringing fsync high will then enable the clocking out of the sdata bits. note that the msb will be clocked out based on the l/ r edge, independent of the state of fsync. miscellaneous nc - no connection, pins 8, 22. these two pins are bonded out to test outputs. they must not be connected to any external component or any length of pc trace. tst -test input, pin 11. allows access to the adc test modes, which are reserved for factory use. must be tied to dgnd. cs5336, cs5338, cs5339 ds23f1 3-57
parameter definitions resolution - the total number of possible output codes is equal to 2 n, where n = the number of bits in the output word for each channel. dynamic range - full scale (rms) signal to broadband noise ratio. the broadband noise is measured over the specified bandwidth, and with an input signal 60db below full-scale. units in decibels. signal-to-(noise plus distortion) ratio - the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. total harmonic distortion - the ratio of the rms sum of all harmonics up to 20 khz to the rms value of the signal. units in percent. interchannel phase deviation - the difference between the left and right channel sampling times. interchannel isolation - a measure of crosstalk between the left and right channels. measured for each channel at the converters output with the input under test grounded and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch - the gain difference between left and right channels. units in decibels. gain error - the deviation of the measured full scale amplitude from the ideal full scale amplitude value. gain drift - the change in gain value with temperature. units in ppm/ c. bipolar offset error - the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below agnd). units in lsbs. cs5336, cs5338, cs5339 3-58 ds23f1
references 1) "a stereo 16-bit delta-sigma a/d converter for digital audio" by d.r. welland, b.p. del sig- nore, e.j. swanson, t. tanaka, k. hamashita, s. hara, k. takasuka. paper presented at the 85th convention of the audio engineering society, november 1988. 2) " the effects of sampling clock jitter on nyquist sampling analog-to-digital converters, and on oversampling delta sigma adc?s" by steven harris. paper presented at the 87th convention of the audio engineering society, october 1989. 3) " an 18-bit dual-channel oversampling delta-sigma a/d converter, with 19-bit mono applica- tion example" by clif sanchez. paper presented at the 87th convention of the audio engineering society, october 1989. ordering guide model resolution passband sclk temperature package cs5336-kp 16-bits 22 khz - active 0 c to 70 c 28-pin plastic dip cs5336-bp 16-bits 22 khz - active -40 to +85 c 28-pin plastic dip cs5338-kp 16-bits 24 khz - active 0 c to 70 c 28-pin plastic dip cs5339-kp 16-bits 24 khz active 0 c to 70 c 28-pin plastic dip cs5336-ks 16-bits 22 khz - active 0 c to 70 c 28-pin soic cs5336-bs 16-bits 22 khz - active -40 to +85 c 28-pin soic cs5338-ks 16-bits 24 khz - active 0 c to 70 c 28-pin soic CS5339-KS 16-bits 24 khz active 0 c to 70 c 28-pin soic cs5336-tc 16-bits 22 khz - active -55 to +125 c 28-pin sidebrazed ceramic dip cdb5336 cs5336 evaluation board cdb5338 cs5338 evaluation board cdb5339 cs5339 evaluation board cs5336, cs5338, cs5339 ds23f1 3-59
features demonstrates recommended layout and grounding arrangements cs8402 generates aes/ebu, s/pdif & cp-340 compatible digital audio buffered serial output interface 16-bit parallel output interface digital and analog patch areas on-board or externally supplied system timing general description the cdb5336, cdb5338 & cdb5339 evaluation boards allow fast evaluation of the cs5336, cs5338 and cs5339 16-bit, stereo a/d converters. the boards generate all converter timing signals and provide both parallel and serial output interfaces. evaluation re- quires a digital signal processor, a low-distortion signal source, and a power supply. also included is a cs8402 digital audio transmitter i.c., which can generate aes/ebu, s/pdif & eiaj cp-340 compatible audio data. the evaluation boards may also be configured to ac- cept external timing signals for operation in a user application during system development. ordering information: cdb5336, cdb5338, cdb5339 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445 7222 fax: (512) 445 7581 aug 93 ds23db5 3-60 evaluation board for cs5336, cs5338 & cs5339 semiconductor corporation cdb5336 cdb5338 cdb5339 cs5336, extclkin ainr ainl sdata sclk serial to parallel converter serial output data parallel output data l/r analog patch area patch area digital power supply regulation & conditioning network offset calibration +5v gnd +15v -15v gnd cs5338, or cs5339 input buffer input buffer clock / timing generator fsync a/d converter cs8402 digital audio line driver digital audio data
power supply circuitry the schematic diagram in figure 1 shows the evaluation board power supply circuitry. power is supplied to the evaluation board by five bind- ing posts. the 5 volt analog power supply inputs of the converter are derived from 15 volts using the voltage regulators u10 and u11. the +5 volt digital supply for the converter and the discrete logic on the board is provided by the +5v and dgnd binding posts. d1, d2 and d4 are transient suppressors which also provide pro- tection from incorrectly connected power supply leads. c25-c28, c30 and c31 provide general power supply filtering for the analog supplies. as shown in figure 2, c10-c13 provide local- ized decoupling for the converter va+ and va- pins. note that c13 is connected between va- and va+ and not va- and agnd. space for a ferrite bead inductor, l1, has been provided so that the board may be modified to power the converters vd+ input directly from the va+ supply. note that the trace connecting the vd+ power to the vd+ of the converter must be bro- ken before l1 may be installed. r5 and c7 low- pass filter the analog logic power supply pin, vl+. the evaluation board uses both an analog and a digital ground plane which are connected at a single point by j1. this ground plane ar- rangement isolates the boards digital logic from the analog circuitry. offset calibration & reset circuit figure 1, shows the optional offset calibration circuit provided on the evaluation board. upon power-up, this circuit provides a pulse on the analog-to-digital converters dpd pin initiating an offset calibration cycle. releasing sw1 also initiates an offset calibration cycle. p6 (see fig- ure 2) selects the signal source used during offset calibration. in the "ain" position, the ainl and ainr inputs are selected during cali- bration, while in the "zero" position, the zerol and zeror inputs are selected. c25 c27 c26 c28 0.22 uf 0.47 uf j1 + c30 47 uf c31 + 47 uf 0.22 uf 78l05 out com u10 in d4 d2 0.47 uf c9 + c8 47 uf 0.1 uf d1 +15v -15v +5v u11 79l05 com in out dgnd agnd va+ va- vd+ d1 = p6ke-6v8p from thomson d2 = d4 = 1n6276a 1.5ke agnd dgnd vd+ 10k c15 0.1uf d3 1n4148 sw1 cal r26 cal (dpd cs5336) 10 11 u7d rst cs8402 8 9 u7e figure 1. power supply and reset circuitry cdb5336,8,9 ds23db5 3-61
cs5336 va- apd dpd acal dcal 5 6 7 9 va+ ainr 27 zerol 3 zeror 26 agnd 1 vd+ vl+ 4 0.1 uf 1 uf vref 28 + 0.1 uf 1 uf + 0.1 uf 51 u1 1 uf + 0.1 uf nc nc 8 22 tst 11 dgnd 19 lgnd 24 10 nf 51 ainl 2 10 nf r4* c4* r3* c3* npo npo c1 c2 r1 r2 25 18 c5 c6 l1 c10 c11 c12 r5 c7 10 p6 ain zero 14 sdata 16 cal sdata l/r c13 vd+ vl+ va+ dcal l/r l/r sdata va- vd+ va+ va- 0.1 uf + c17 c16 10 uf cal cmode smode r7 12 13 20 k vd+ sclk 15 sclk sclk fsync 17 fsync fsync iclkd oscillator module c15 0.1 uf 8 12.288 mhz 7 14 vd+ nc 1 p7 ext r6* clkin 20 oclkd iclka iclka 21 23 vd+ 1 2 714 mck 8402 3 c14 0.1 uf u8a iclkd ext int 10 nf 10 nf 51 51 51 75 * optional u3 pins 1,13 u9 from buffers fig 3 cs5338 cs5339 figure 2 adc connections cdb5336,8,9 3-62 ds23db5
analog inputs as shown in figure 2, the analog input signals are connected to the cs5336 via an rc network. r1 and c1 provide antialiasing and optimum source impedance for the right analog input channel while r2 and c2 do so for the left chan- nel. the zeror and zerol inputs are tied to the analog ground plane on the board as shipped from the factory, but space is provided for an op- tional rc section on each. these rc sections may be added to model the output impedance of the analog signal source to minimize offset error during calibration. figure 3 shows the optional input buffer circuit. this can be used as an example input buffer cir- cuit for your application. if the adc is driven from a 50 w source impedance signal generator, the input buffer amplifiers may be bypassed. place p8 and p9 jumpers in the out position, and short circuit r1 and r2. this ensures that the adc is driven from a 50 w source resis- tance. also remove u13 op-amp, to remove the 1k w load impedance. timing generator p7 selects the master clock source supplied to the iclkd pin of the converter. as shipped from the factory, p7 is set to the "int" position to select the 12.288 mhz clock signal provided by u3. an external master clock signal may be con- nected to the extclkin connector and selected by placing p7 in the "ext" position. note that r6, tied between extclkin and gnd, is available for impedance matching an external clock source. the board is shipped with smode high, which selects master timing mode. in this mode, sclk, l/ r and fsync are all out- puts, generated by the converter from iclkd. serial output interface the serial output interface is provided by the sdata, sclk, fsync and l/ r b nc connectors on the evaluation board. these out- _ + u13a va+ 0.1 uf 8 1 k r22 4 va- 0.1 uf 1 2 3 1 k r21 r1, fig 2 u13b 1 k r24 7 6 5 1 k r23 r2, fig 2 ainl ainr in out in out p9 p8 c32 c33 _ + mc33078p figure 3. input buffer circuit cdb5336,8,9 ds23db5 3-63
puts are buffered, as shown in figure 5, in order to isolate the converter from the digital signal processor. if slave mode is selected by pulling smode low, then u9 (74hc243) will change to the opposite direction, and act as an input buffer. u9 is provided to protect against inadvertent ex- ternal driving of sclk, l/ r and fsync while in master mode. u9 is not necessary in your application circuit. jumper p4 allows the board to be configured for either the cs5336/38, or the cs5339, which have opposite polarities of sclk. parallel output interface figure 6 depicts the parallel output interface on the evaluation board. 16-bit words are assembled from the serial data output of the converter. each bit of serial data is clocked out of the converter vd+ mck sck pro fsync sdata gnd v c u m0 m1 m2 cs8402 u2 c7/c3 c1/fc0 c6/c2 c9/c15 em1/c8 em0/c9 cre/fc1 rst txp txn cbl u8d vd+ 142567893 10 k sip 2 1 3 4 12 13 14 24 rst ___ 20 17 r20 24 1 3 r19 110 oclkd p4 56 c24 0.1 uf c34 1 uf + r18 20 k r17 r16 20 k 20 k q2 q2 reset2 d2 clk set2 13 9 12 11 10 8 +5 v r11 47 k __ l/r cs5336 fsync cs5336 7 74hc74 u12b cs5336 fsync sdata 12 13 11 74hc08 21 22 23 9 10 11 15 18 19 8 ____ __ __ __ ___ __ __ __ __ __ ____ p3 cbl v c u 16 3 2 4 5 6 8 7 1 14 15 13 12 11 9 10 16 _ digital output dipsw 8 sw 2 vd+ pulse pe65612 schott 67125450 vd+ figure 4. cs8402 digital audio line driver connections cdb5336,8,9 3-64 ds23db5
on the rising edge of sclk and shifted into the 16-bit shift register formed by u4 and u5 on sclks falling edge. after all data bits for the selected channel have been shifted into u4 and u5 the data is latched onto p1 by a delayed ver- sion of fsync. p5 selects the channel whose output data will be converted to parallel form and presented on p1. with p5 in the "b" (both) position, parallel data from one channel will be presented first with data from the other channel presented sub- sequently. in the "l" (left) position, only left channel conversions will be presented, while in the "r" (right) position only right channel con- versions are presented. two interface mechanisms are provided for read- ing the data from this port. with the first, the edges of l/ r may be used to clock the parallel data into the digital signal processor. (set jumper p2 into the l/ r position.) alternatively, a hand- shake protocol implemented with dack and drdy may be used to transfer data to the signal processor. (set jumper p2 to the drdy posi- tion.) the fall of drdy informs the digital signal processor that a new data word is avail- able. the processor then reads the port and acknowledges the transfer by asserting dack. note that drdy will not be asserted again un- less dack is momentarily brought high although new data will continue to be latched onto the port. digital audio standard interface included on the evaluation board is a cs8402 digital audio line driver. this device can im- plement aes/ebu, s/pdif and eiaj cp-340 interface standards. figure 4 shows the sche- matic for the cs8402. p3 allows the c, u and v bits to be driven from external logic using the cbl output for block synchronization. sw2 pro- vides 8 dip switches to select various modes and bits for the cs8402. table 3 lists the settings for the professional mode which is the default setting for the evaluation board from the factory. the third switch selects between professional u9 a-to-b b-to-a a4 b4 vcc gnd b1 b2 b3 vd+ a1 a2 a3 sclk fsync l/r enable enable 13 vd+ r8 20 k smode sclk fsync sdata r9 20 k r10 20 k 9 10 11 1 13 14 7 3 4 5 8 6 15 17 14 16 910 8 u8c vd+ sdata sdata sdata l/r l/r fsync sclk 74hc08 74hc243 0.1 uf c20 u8b 4 5 6 5336/38 5337/39 34 u7b pin 11 u4, u5 595's cs8402 pin 6 p4 figure 5. serial output interface cdb5336,8,9 ds23db5 3-65
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) dack 13 13 oe q h g q f q e q d q c q b q a q u4 74hc595 7 6 5 4 3 2 1 15 14 oe q h g q f q e q d q c q b q a q din 7 6 5 4 3 2 1 15 c16 11 shift clk u5 74hc595 (msb) vd+ 16 vcc 8 gnd 10 srclr 12 latch clk 11 shift clk 12 latch clk 10 srclr 8 gnd vd+ 16 vcc 14 din 9 dout dout 9 1 2 u7a 74hc14 p2 vd+ r12 sdata c17 0.1uf 0.1uf drdy drdy vd+ 7 14 0.1uf c18 l/r l/r 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 vd+ r15 z x y x z y rp2 68 dip resistor rp3 68 dip resistor 4 vd+ r11 47k vd+ 0.1 uf clk u6a 74hc74 d 3 2 6 5 pre 1 clr q q c19 7 14 clk u6b 74hc74 d pre clr q 10 11 12 13 8 9 q pin17 pin20 fsync iclkd u1 u1 u12a clr pre gnd vcc q d vd+ 0.1 uf q r11 47 k 47 k vd+ l/r pin14 u1 2 3 47 14 6 5 1 b l r vd+ 47k 68 r13 68 r14 p5 65 u7c c29 p1 p4 clk figure 6. parallel output interface cdb5336,8,9 3-66 ds23db5
input/output connector signal present +15 -15 agnd ainl ainr sdata input output output/input input input input input +15 volts from power supply -15 volts from power supply analog ground connection from power supply left channel analog input right channel analog input left /right channel signal serial output data sclk output/input serial output clock extclkin external master clock input input l/r dgnd input digital ground connection from power supply +5 input +5v for adc vd+ and discrete logic digital output output cs8402 digital output via transformer fsync output/input data framing signal p3 output/input cs8402 c,u,v inputs; cbl output p1 output parallel output data p6 p7 p5 p2 jumper purpose position function selected selects channel for serial to parallel conversion selects master clock source for cs5326 clkin selects offset calibration input source offset calibration ainl and ainr selected during zerol and zeror selected during offset calibration clkin provided by u3 clkin provided by extclkin bnc left channel data presented on p1 right channel data presented on p1 left then right channel data alternately presented on p1 ain *zero *l r b *drdy l/r *int ext * default setting from factory selects l/r or drdy as the output status signal presented on p1 drdy selected to signal the arrival of new data for the selected channel l/r selected p8, p9 selects optional input buffers *in out buffer amplifier in circuit buffer amplifier bypassed p4 selects device type 5337/39 5336/38 correct sclk for cs5337 & cs5339 correct sclk for cs5336 & cs5338 table 2. jumper selectable options table 1. system connections cdb5336,8,9 ds23db5 3-67
and consumer modes; however, the cs8402 out- put to the transformer must be modified, as shown below table 4, to be compatible with the consumer interface. table 4 lists the switch set- tings for consumer mode. if the c input of connector p3 is used, the input bits are logically ored with the appropriate dip switch bits. in tables 3 and 4, the c bits listed in the com- ment section are taken from the digital audio interface specifications. as an example, switch 6 in the professional mode (table 3) controls c9 which is the inverse of channel status bit 9 (also listed as byte 1, bit 1 in the cs8402 data sheet). channel status bit 9 is one of four bits indicating channel mode. therefore, using dip switch 6, only two of the available channel modes may be selected. the c input port on connector p3 may be used to select other channel modes. see the cs8401 & cs8402 part data sheet for more in- formation on the operation of the cs8402. switch# 0=closed, 1=open comment 3 pro=0 professional mode, c0=1 (default) 1 cre local sample address counter & reliability flags default 0 disabled 1 internally generated (channel status bytes 14-17 and byte 22) 5, 2 c6, c7 c6,c7 - sample frequency 1 1 00 - not indicated - default to 48 khz default 1 0 01 - 48 khz 0 1 10 - 44.1 khz 0 0 11 - 32 khz 4 c1 c1 - audio default 1 0 - normal audio 0 1 - non-audio 6 c9 c8,c9,c10,c11 - channel mode (1 of 4 bits) 1 0000 - not indicated - default to 2-channel default 0 0100 - stereophonic 8, 7 em1, em0 c2,c3,c4 - emphasis default 1 1 000 - not indicated - default to none 1 0 100 - no emphasis 0 1 110 - 50/15 m s 0 0 111 - ccitt j.17 table 3. cs8402 switch definitions - professional mode cdb5336,8,9 3-68 ds23db5
switch# 0=closed, 1=open comment 3 pro=1 consumer mode, c0=0 (note 1) 1, 4 fc1, fc0 c24,c25,c26,c27 - sample frequency (encoded 2 of 4 bits) 0 0 0000 - 44.1 khz 0 1 0100 - 48 khz 1 0 1100 - 32 khz 1 1 0000 - 44.1 khz, cd mode 2 c3 c3,c4,c5 - emphasis (1 of 3 bits) 1 000 - none 0 100 - 50/15 m s 5 c2 c2 - copy/copyright 1 0 - copy inhibited/copyright asserted 0 1 - copy permitted/copyright not asserted 6 c15 c15 - generation status 1 0 - definition is based on category code. 0 1 - see cs8402 data sheet, appendix a 8, 7 c8, c9 c8-c14 - category code (2 of 7 bits) 1 1 0000000 - general 1 0 0100000 - pcm encoder/decoder 0 1 1000000 - compact disk - cd 0 0 1100000 - digital audio tape - dat note: 1. the evaluation board is shipped from the factory in the professional mode. changing switch 3 to open places the cs8402 in consumer mode; however, the hardware is not set up for consumer mode. to modify the hardware for consumer mode, change r19 to 374 w and add r20 at 90.9 w . then, as shown in the figure below, cut the trace connecting txn to the transformer, and connect the transformer side to the ground hole provided. for a full explanation of the consumer hardware interface, see the cs8402 data sheet, appendix b. table 4. cs8402 switch definitions - consumer mode cs8402 u2 txp txn 20 17 r20 24 1 3 r19 digital output pulse pe65612 schott 67125450 90.9 374 cdb5336,8,9 ds23db5 3-69
figure 7. top ground plane layer (not to scale) cdb5336,8,9 3-70 ds23db5
figure 8. bottom trace layer (not to scale) cdb5336,8,9 ds23db5 3-71
figure 9. component layout (not to scale) cdb5336,8,9 3-72 ds23db5

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